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[VHDL-FPGA-Verilog] verilog实例

Description: 一些很实用的verilog源程序，是初学者的好棒手，希望能给需要的人一点帮助，请支持一下。-some very practical Verilog source is the beginners excellent hands, in hopes of giving those who need a bit of help, please support what.
Platform: | Size: 165888 | Author: 叶若寒 | Hits:

[VHDL-FPGA-Verilog] fifo程序

Description: 用verilog语言在fpga中实现fifo功能！-using Verilog language in which they simply realize fifo function!
Platform: | Size: 1024 | Author: 刘涛 | Hits:

[ARM-PowerPC-ColdFire-MIPS] modlesim的一个简单教程

Description: fpga仿真软件的一个很好的中文教材,对系统的仿真特别时序,是很好的工具-a good Chinese language teaching system, the particular timing simulation is a good tool
Platform: | Size: 505856 | Author: guo | Hits:

[Other Embeded program] pcit32_verilog_lattice

Description: 本文件是pci的verilog源代码程序-pci the Verilog source code procedures
Platform: | Size: 430080 | Author: 王立华 | Hits:

[VHDL-FPGA-Verilog] scu_all_fpga

Description: 大型嵌入式设备FPGA程序，verilog HDL语言，实现DLL和PCM码流分流。-large embedded FPGA procedures, Verilog HDL, DLL and achieve PCM stream diversion.
Platform: | Size: 3072 | Author: chenlei | Hits:

[VHDL-FPGA-Verilog] pro001_buzzer

Description: 使用FPGA控制蜂鸣器的程序,用Verilog HDL设计,可以是蜂鸣器发出各种不同的声音-FPGA use buzzer control procedures, using Verilog HDL design, it is the buzzer sounded different voices
Platform: | Size: 779264 | Author: wpb3dm | Hits:

[VHDL-FPGA-Verilog] Altera_uart_Verilog

Description: FPGA/CPLD应用,uart的Verilog HDL原码-FPGA/CPLD applications, UART Verilog HDL source
Platform: | Size: 10240 | Author: cyberworm | Hits:

[Static control] clock2001

Description: 时钟模块之一：二进制转BCD码verilog源代码FPGA advantage编程环境-clock module : BCD switch binary source code Verilog FPGA advantage programming environment
Platform: | Size: 1024 | Author: dandan | Hits:

[Compress-Decompress algrithms] i2c(FPGA)

Description: 基于FPGA的I2C总线模拟，采用verilog HDL语言编写。-FPGA-based I2C bus simulation, using verilog HDL language.
Platform: | Size: 212992 | Author: 李浩 | Hits:

[Compress-Decompress algrithms] canbus(FPGA)

Description: 基于FPGA的can 总线设计，采用verilog语言编写。在FPGA的开发环境下，新建一个工程，然后将本文件中的各个源代码添加进工程里，即可运行仿真。-FPGA-based bus design can use verilog language. FPGA development environment, a new project, and then the paper all the source code to add the project, Simulation can be run.
Platform: | Size: 862208 | Author: 李浩 | Hits:

[VHDL-FPGA-Verilog] ModelSim6c_SE_Cracker

Description: crack for ModelSim, a Verilog, VHDL and mixed VHDL / Verilog CAD simulator for FPGA, board and IC design.-crack for ModelSim, a Verilog. VHDL and mixed VHDL/Verilog simulator for CAD F PGA, board and IC design.
Platform: | Size: 292864 | Author: 陈亨利 | Hits:

[VHDL-FPGA-Verilog] SPI_verilogHDL

Description: 本原码是基于Verilog HDL语言编写的，实现了SPI接口设计，可以应用于FPGA,实现SPI协议的接口设计.在MAXII编译成功,用Modelsim SE 6仿真成功.-primitive code is based on Verilog HDL language, and achieving the SPI interface design, FPGA can be used to achieve agreement SPI interface design. MAXII success in the compiler, Modelsim SE with six successful simulation.
Platform: | Size: 1024 | Author: jevidyang | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 利用FPGA实现浮点运算的verilog代码 希望能够给需要做这方面研究的同仁有所帮助-use FPGA floating-point operations verilog code hope to be able to do this to the need for research in the Tongren help
Platform: | Size: 130048 | Author: jake | Hits:

[Other Embeded program] turbo[1].tar

Description: turbo码的verilog程序，有意者请下载。-turbo code verilog procedures Interested parties please download.
Platform: | Size: 84992 | Author: liu | Hits:

[VHDL-FPGA-Verilog] add_16_pipe

Description: 16位加法器的流水线计算,verilog代码，用于FPGA平台。-16 pipelined adder, verilog code for the FPGA platform.
Platform: | Size: 1024 | Author: qjyong | Hits:

[VHDL-FPGA-Verilog] verilog-som

Description: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Platform: | Size: 5120 | Author: 刘索山 | Hits:

[VHDL-FPGA-Verilog] mouse_control

Description: 1、 用FPGA实现PS/2鼠标接口。 2、 鼠标左键按下时十字形鼠标图象的中间方块改变颜色，右按下时箭头改变颜色。 3、 Reset按键：总复位。 -one with FPGA PS/2 mouse interface. 2, the left mouse button pressed cruciform images in the middle mouse to change the color box, press the right arrow at the change in color. 3, Reset buttons : the total reduction.
Platform: | Size: 9216 | Author: lee | Hits:

[VHDL-FPGA-Verilog] ClockOut

Description: 通过VERILOG编程，实现FPGA任意整数分频的源代码-through verilog programming, FPGA arbitrary integer frequency of the source code
Platform: | Size: 1024 | Author: 田世坤 | Hits:

[VHDL-FPGA-Verilog] usb_2

Description: usb2的FPGA实现，verilog语句-usb2 FPGA, verilog statement
Platform: | Size: 196608 | Author: lious | Hits:

[Windows CE] DDSFPGA_cylone

Description: dds设计，花了一个星期做的,verilog写的，可生成多种波形，频率范围可上M,性能不错。-dds design, spent a week doing, verilog written, multiple waveform generation, frequency range available on the M, good performance.
Platform: | Size: 637952 | Author: 苏纳 | Hits:
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